1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method therefor and, more particularly, to a semiconductor device having a LOC structure and a manufacturing method therefor.
2. Description of the Prior Art
FIG. 1A is a sectional view of a semiconductor device having a conventional LOC structure, and FIG. 1B is a plan view of the same. This structure is effective for accommodating a large-capacity, multi-functional, large-size semiconductor element (to be referred to as a chip hereinafter) in a package. As shown in FIGS. 1A and 1B, a chip 2 is fixed to the lower surfaces of inner leads 1a of a semiconductor device lead frame 1 (to be referred to as a lead frame hereinafter) by insulating adhesive tapes 6 such that its circuit-formed surface faces the insulating tapes 6. Electrodes 3 (to be referred to as pads hereinafter) on the chip 2 and the inner leads 1a are electrically connected to each other in accordance with wire bonding using gold wires 8 (to be referred to as wires hereinafter).
Reference numeral 7 denotes an encapsulating resin that hermetically encapsulates the chip 2.
In this conventional LOC structure, the connecting shape (to be referred to as the loop shape hereinafter) of the wires 8 is such that the wires 8 extend above the inner leads 1a, as shown in FIG. 1A, and has a height of several ten to several hundred plus .mu.m, which interferes with meeting a demand for a lower-profile semiconductor device.
FIG. 2 is a perspective view of the internal structure of a semiconductor device having a conventional LOC structure disclosed in, e.g., Japanese Unexamined Patent Publication No. 2-246125. Referring to FIG. 2, pads 13 including power supply pads, ground pads, and signal pads are arranged in an array at the center of the circuit-formed surface of a large-size chip 11 encapsulated with an encapsulating resin 12 along the longitudinal direction.
A plurality of power supply pads and a plurality of ground pads are arranged in order to reduce electric noise. A plurality of leads 14 extend onto the chip 11, and the leads 14 and predetermined pads 13 are electrically connected to each other through wires 15.
Leads 16 at the two ends of the chip 11 in the longitudinal direction thereof are connected to each other (these leads will be referred to as common leads hereinafter). The common leads 16 are used as power supply leads and ground leads that are connected to the pads 13 at a plurality of portions. The signal leads 14 among the plurality of leads 14, and the signal pads 13 are electrically connected to each other through wires across the common leads 16.
FIG. 3 is a sectional view of a semiconductor device using TAB (Tape Automated Bonding) tapes. In this structure, a chip 2 is fixed to the lower surfaces of TAB tapes 5 that hold TAB leads 4. One end of each TAB lead 4 and a corresponding pad 3 of the chip 2 are electrically connected to each other, and the other end of each TAB lead 4 projects from an encapsulating resin 7 to extend to the outside.
Japanese Unexamined Patent Publication No. 5-82585 discloses a semiconductor device using TAB tapes and TAB leads. In this semiconductor device, pads and the TAB leads are connected to each other, and a plurality of power supply pads and a plurality of ground pads can be connected to the TAB leads. This improves the electrical characteristics of the semiconductor element.
In the semiconductor device having the conventional LOC structure shown in FIGS. 1A and 1B, the leads 1a and the pads 3 are connected to each other through the wires 8. Due to limitations on the manufacturing method, the wires 8 must have a certain loop height. Accordingly, it is very difficult to meet a recent demand for a lower-profile semiconductor device.
In the semiconductor device having the conventional LOC structure shown in FIG. 2, it is indispensable to connect the plurality of power supply pads 13 and the plurality of ground pads 13 that aim at improving the electrical characteristics, e.g., a decrease in power supply noise, to the power supply leads 16 and the ground leads 16, so that the packaging degree and the number of functions of the semiconductor device increase. However, other signal pads 13 and other leads 14 must be connected to each other through wires 8 across the common leads 16. For this purpose, the loop height must be increased accordingly so that the wires 8 and the common leads 16 may not come into contact with each other. Therefore, the semiconductor device cannot have a low profile.
In order to manufacture products having different functions by using the same chips and to reduce the manufacturing cost of semiconductor devices, at least one or more pads that effect diversion into different products are arranged on the chip. Different combinations of connection of these pads with power supply leads or ground leads allow diversion into several types of products. An example of the difference in product function includes the count of data that can be input/output simultaneously in the case of DRAMs.
Conventionally, these pads and leads are connected to each other by wire bonding, which will be described with reference to FIG. 4. Assume that in order to manufacture a product having a function of type I, a lead 1c must be connected to pads 3b and 3c.
Assume that in order to manufacture a product having a function of type II by using the same chip as that used for type I products, the lead 1c must be connected to pads 3a and 3d. In this case, a wire 8 that connects the lead 1c and pad 3d extends above a lead 1d adjacent to the lead 1c, and the lead 1d and the wire 8 may contact each other. Therefore, connection of the lead 1c and the pad 3d through the wire 8 becomes impossible.
Therefore, in order to manufacture the products of types I and II, separate lead frames must be prepared considering the different pad arrangements and wire bonding. Even though the same chips are used, several types of lead frames must be prepared. This hinders use of a common lead frame.
In the semiconductor device shown in FIG. 3 which uses the TAB tapes 5 and the TAB leads 4 and realizes a low profile, the TAB leads 4 extending to the outside of the package deform easily as they are metal foils having a thickness of about several ten .mu.m. This semiconductor device is very difficult to handle during the manufacture or when being mounted on a board.